1. Field of the Invention
The invention relates to a pipelined analog-to-digital converter (ADC), and more particularly to a pipelined analog-to-digital converter comprising a multiplying digital-to-analog converter (MDAC).
2. Description of the Related Art
The analog-to-digital conversion process converts an analog signal, which is most commonly represented as a voltage, into a digital format. Well-known analog-to-digital conversion methods include series, delta-sigma, parallel, and pipelined architecture. Different architectures are suited for different needs.
A series analog-to-digital architecture provides a wide performance range in analog-to-digital conversion, offering low power consumption and low resolution to quantization. A series architecture typically quantizes analog data at the rate of one bit per cycle. Therefore, a digital sample having N bits of resolution will take N cycles to complete quantization.
A delta-sigma analog-to-digital architecture is often used in audio signal processing. The architecture is designed to translate high-speed, low-resolution samples into higher-resolution, lower-speed outputs. This process is also referred to as oversampling because more samples of the analog data are quantized than actually outputted.
By contrast, a parallel analog-to-digital architecture provides the fastest quantization rate per analog signal. For a parallel (or “flash”) architecture, a digital value per cycle is produced for each analog data sample, without regard to N, the number of bits of resolution. A parallel architecture requires that all quantization levels be simultaneously compared to the analog signal. This results in the use of 2(N−1) comparators and 2(N+1) resistors to achieve a digital value, with N bits of resolution, per cycle. For higher resolution, the circuit complexity of the flash analog-to-digital converter will greatly increase.
Pipelined analog-to-digital architecture, like series analog-to-digital architecture, is a method of quantizing an analog signal in stages. Algorithms exist for obtaining either 1 or 1.5 bits of resolution per stage. In a 1.5-bit per stage converter, the digital output Di of each stage is either 1, 0, or −1. In a 1-bit per stage converter, the digital output of each stage is either 1 or −1 (or 1 or 0). For either algorithm, N stages are used for an N-bit digital value. For resolution of a following bit, one bit is first resolved at each stage, and a residual analog signal sample is transmitted to the following stage for resolution of another bit.